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TPS23757
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PIN FUNCTIONS
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
NAME
CTL
NO.
1
TYPE
I
DESCRIPTION
The control loop input to the PWM (pulse width modulator), typically driven by output regulation feedback (e.g.
optocoupler). Use V B as a pullup for CTL.
V B
CS
COM
GATE
V C
2
3
4
5
6
O
I/O
O
I/O
5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 μ F to ARTN.
DC/DC converter switching MOSFET current sense input. See R CS in Figure 1 .
Gate driver return, connect to ARTN, and RTN for most applications.
Gate drive output for the main dc/dc converter switching MOSFET.
DC/DC converter bias voltage. Connect a 0.47 μ F (minimum) ceramic capacitor to ARTN at the pin, and a
larger capacitor to power startup.
GAT2
ARTN
RTN
V SS
V DD1
V DD
7
8
9
10
11
12
O
I
I
Gate drive output for a second dc/dc converter switching MOSFET (see Figure 1 ).
ARTN is the dc/dc converter analog return. Tie to COM, and RTN for most applications.
RTN is the output of the PoE hotswap MOSFET.
Connect to the negative power rail derived from the PoE source.
Source of dc/dc converter startup current. Connect to V DD for many applications.
Connect to the positive PoE input power rail. V DD powers the PoE interface circuits. Bypass with a 0.1 μ F
capacitor and protect with a TVS.
DEN
13
I/O
Connect a 24.9 k ? resistor from DEN to V DD to provide the PoE detection signature. Pulling this pin to V SS
during powered operation causes the internal hotswap MOSFET to turn off.
PPD
14
I
Raising V PPD - V VSS above 1.55 V enables the hotswap MOSFET and activates APb. Connecting PPD to V DD
enables classification when APD is active. Tie PPD to V SS or float when not used.
CLS
DT
15
16
I
I
Connect a resistor from CLS to V SS to program classification current per Table 1 .
Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to V B to disable GAT2
operation.
APD
17
I
Raising V APD -V ARTN above 1.5 V disables the internal hotswap MOSFET, turns class off, and forces APb
active. This forces power to come from a external V DD1 -V RTN adapter. Tie APD to ARTN when not used.
BLNK
18
I
Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor from BLNK to
ARTN to program a more accurate period.
FRS
19
I
Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be used to
synchronize the converter to an external timing source.
APb
20
O
Active low output that indicates PPD (first level) or APD are active.
PIN DESCRIPTION
See Figure 1 for component reference designators (R CS for example), and the Electrical Characteristics table for
values denoted by reference (V CSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD (adapter priority detect) forces power to come from an external adapter connected from V DD1 to RTN by
opening the hotswap switch, disabling the CLS output (see PPD pin description), and enabling the APb output. A
resistor divider is recommended on APD when it is connected to an external adapter. The divider provides ESD
protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification
assures the adapter output voltage is high enough that it can support the PD before the PoE current is cut off.
Select the APD divider resistors per Equation 1 where V ADPTR-ON is the desired adapter voltage that enables the
APD function as adapter voltage rises.
R APD1 APD2 ′
=R
( V ADPTR_ON
- V APDEN
) V APDEN
R APD1 APD2
V ADPTR_OFF =
+R
R APD2
′
( V APDEN
- V APDH )
(1)
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.
Copyright ? 2009–2013, Texas Instruments Incorporated
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